1. Field of the Invention
The invention relates to an ion implantation method, and more particularly, to an ion implantation method for adjusting the threshold voltage of MOS transistors.
2. Description of the Prior Art
The metal-oxide semiconductor (MOS) transistor is an electric component commonly used in integrated circuits. MOS transistors are four-connecting-point components composed of a gate, a source and a drain.
Please refer to FIG. 1. FIG. 1 is a perspective diagram of a prior art MOS transistor 40 on a semiconductor wafer 10. The MOS transistor 40 comprises a gate 22, source 30 and drain 32. Shallow trenches 14 or FOX (field oxide) positioned around the MOS transistor 40 isolate it from other components.
Please refer to FIG. 2 to FIG. 4. FIG. 2 to FIG. 4 are perspective diagrams of producing the MOS transistor 40 in FIG. 1. First, shallow trenches 14 are formed on the P-type Si substrate 12 of the semiconductor wafer 10. Dopants B.sup.11 or BF.sub.2.sup.+ are implanted in areas surrounding the shallow trenches 14 to form an impurity region 16. This is accomplished by ion implantation at a threshold voltage V.sub.t and dosage of 5.times.10.sup.11.about.5.times.10.sup.12 atoms/cm.sup.2. Then, thermal oxidation is performed to form a 40.about..RTM..ANG. silicon oxide layer on the surface of the Si substrate 12 followed by in-situ phosphorus doped LPCVD to form a 500.about.1000 .ANG. poly-silicon layer on the surface of the silicon oxide layer. The silicon oxide layer and poly-silicon layer are etched by photolithography and etching to severally form a gate insulating layer 18 and gate conducting layer 20 with rectangular-shaped cross sections. This completes formation of the gate 22.
Then, an ion implantation process is performed to implant dopants P.sup.31 or As.sup.75 to form an N.sup.- lightly doped source 24 and drain 26 between the gate 22 and shallow trenches 14. A spacer 28 is then formed at two sides of the gate 22. Then, another ion implantation process is performed to implant dopants As.sup.75 to form an N.sup.+ heavily doped source 30 and drain 32 between the spacer 28 and shallow trenches 14. This completes the formation of the MOS transistor 40 of N-channel shown in FIG. 1.
As the size of the memory cell of the dynamic random access memory (DRAM) gets smaller, the width between the channel below the gate 22 of the MOS transistor 40 and the spacer 28 is smaller. Therefore, the impurity concentration of the impurity region 16 increases in proportion.
The impurity dosage required to form the source and drain is much greater than the dosage required to adjust the threshold voltage. When the dosage to adjust the threshold voltage is increased, the dosage of the source and drain is increased proportionately. However, as the dosage of the source and drain is increased, the junction leakage and junction capacitance of the MOS transistor 40 is greatly increased. But, when the dosage of the source 24 and drain 26 is decreased, the saturated drain current (I.sub.dsant) of the MOS transistor is reduced which makes it difficult for the capacitance of the memory cell of DRAM to read and write signals.